Use of accelerator devices, such as field-programmable gate arrays (FPGAs), in data centers is increasing to a point where more memory needs to be available for the accelerator devices to access and to allow for more fluid operations between individual accelerator devices. Presently, compute devices with one or more accelerator devices contain memory devices that are local to the accelerator devices on the compute device, and are inaccessible to other accelerator devices. That is, a memory device is only utilized by a single accelerator device coupled to the memory device within the compute device.
The implementation of the memory devices among the individual accelerator devices described above leads to difficulty in spreading workloads (e.g., applications, processes, etc.) across multiple accelerator devices, as any data sets to be operated on are only accessible to a single accelerator device. As such, for data centers that include many accelerator devices, a large number of the accelerator devices may be unused at any given time, as they are unable to share in the execution of a workload with other accelerator devices.